In general, the digital phase differentiator (DPD) is a frequency modulation (FM) demodulation method that requires a hard limited signal at an intermediate frequency as input and outputs a baseband discriminator signal. The DPD is part of an integrated digital controller ademodulation chip. The DPD receives the limited signal from a back-end receiver chip that does the intermediate frequency filtering that gives the radio the desired selectivity.
As shown in FIG. 1, the DPD is basically a detector which obtains the phase of the limited signal and a differentiator that estimates the FM demodulation process. The intermediate frequency (Fif) limited input is buffered and synchronized to the system clock Fs 10 (e.g., 16.8 MHz). The synchronized limited signal 12 is used to trigger or capture the counter 14 at a particular state. The period of the counter is setup so that it is an exact integer multiple of the Fif. Therefore, when there is no modulation on the limited signal, the synchronized limited signal will capture the same counter value at every rising edge of the limited signal. When there is modulation on the limited signal, the phase register 15 value will represent the phase of the signal. As mentioned, the period of the counter 14 must be an integer multiple of the Fif. The integer multiple used or the size of the counter 14 is determined by the occupied bandwidth of the signal. The phase signal at the phase register 15 output is then sub-sampled at some convenient rate.
The last stage of the DPD is a differentiator 17 which is approximated by a difference function. The differentiator 17 consists of a N-delay stage 16 and a modulo subtractor 18. The modulo subtractor 18 is required because the phase is modulo, wherein the term modulo means the maximum number of states for a counter. The N-delay stage 16 determines the time constant of the differentiation. This output is equivalent to a sampled discriminator. The output is then fed to a normal demodulation block for further processing of the signal to convert the signal into bits.
Due to odd sampling rates of a practical DPD system, there will be an offset between the desired input limited signal frequency (e.g., 455 KHz) and the desired Fif of the DPD. This offset causes DPD system performance degradation. The sampling rates of a DPD system are required to be integer multiples of the reference oscillator frequency and correspondingly the system clock Fs 10. Also, the Fif of the input limited signal should be restricted to standard frequencies (e.g., 455 KHz) to take advantage of the high volume parts that are already being produced.
Some examples of DPD sampling frequencies and counter periods (also called "divider"), assuming a reference oscillator frequency of 16.8 MHz and an Fif of 455 KHz, are as follows:
1. sampling at 16.8/2=8.4 MHz with a counter period of 18 yields a DPD Fif of 466.7 KHz; and PA1 2. sampling at 16.8/3=5.6 MHz with a counter period of 12 yields a DPD Fif of 466.7 KHz.
As stated, the desired Fif of the DPD is 466.7 KHz and the desired input limited signal frequency is 455 KHz, thus there is 11.7 KHz of difference between the two signals. The frequency offset between the Fif of the DPD and the input limited signal frequency is usually unavoidable. This frequency offset causes degradation in the performance of the DPD. As a result, with an offset of 11.7 KHz, at least 1 dB of system degradation occurs which is not tolerable in a feasible DPD system.
A first solution to the magnitude of the offset problem is to use a different Fif which usually entails custom filters. A second solution to the magnitude of the offset problem is the addition of special crystals to provide the necessary reference oscillator frequency. However, such use of customized filters or special crystals increases the product cost and increases the power consumption. Alternatively, a third solution to the magnitude of the offset problem is to do nothing and live with a performance which is not acceptable.
Hence, there exists a need for a method and apparatus to allow DPD sampling frequency and counter period to yield a DPD Fif closer to the desired input limited signal frequency without increasing either the product cost or the power consumption.